The present invention relates to the compiling of a source program, and more particularly to a method for generating an object program suitable for improving an execution speed to a DO loop which contains a branch instruction.
A vector processor has a vector processing unit which processes a set of array data in a block. One example of such vector processor is Hitachi S-810. The vector processor has a function to execute a one-dimension parallel operation instruction called a vector instruction under a pipeline control.
For example, in a FORTRAN source program, an iterative operation such as
DO 10 I=1, N PA1 10 Z(I)=X(I) +Y(I) PA1 Z(1:N)=X(1:N)+Y(1:N) PA1 DO 10 I=1, N PA1 IF (A(I), GT, B(I)) THEN Z(I)=X(I) +Y(I) PA1 ENDIF PA1 10 CONTINUE PA1 C(1:N)=A(1:N).multidot.GT.multidot.B(1:N) PA1 Z(1:N)=X(1:N)+Y(1:N) PA1 if C(1:N)=true
can be executed by one vector instruction
which instructs to place a sum of elements 1-N of an array X and elements 1-N of an array Y, into elements 1-N of an array Z. The conversion to such a vector instruction is called vectorizatoon and the array data X, Y, Z are called vectors.
When the DO loop contains an IF clause, for
it can be executed by the vector processor by the following control vector method. In a hardware aspect, a control vector C is introduced in addition to the vectors X, Y and Z which are direct objects of operation, and operations between Xi and Yi are controlled depending on whether a bit Ci of C is "0" or "1". A principle of operation when the vector instruction described above is under control of the control vector C is explained below.
A control vector generation instruction and two vector instructions for calculating Z under control of the control instruction are executed.
If a value of an i-th element of an array A is larger than a value of an i-th element in an array B, an i-th element of the control vector C is set to true (1) and the above process is repeated for i=1-N. Only when the i-th element of the control vector C is true (1), a sum of the value of the i-th element of the array X and the value of the i-th element of the array Y is stored into the i-th element of the array Z. The above step is repeated for i=1-N. Thus, a result obtained by looping a scalar process and the result obtained by executing those two vector instructions are equal. In this manner, the loop which contains a conditional branch clause can be vectorized.
A compiler determines whether the DO loop can be converted to the vector instruction based on a sequence/data dependence of setting (definition) of arrays and variables in the source program and use (reference) of the arrays and variables.
The above vector processor or compiler technique is disclosed in "Super Computers, Class VI Systems, Hardware and Software" published by Elserier Science Publishers B. V. (North Holland), pages 113-135, and "Hitachi Super Computer S-810 Array Processor System".
In the prior art system described above, if the loop contains a conditional branch instruction and if the loop resulted in disordering of a sequence of definition and reference of data by converting to a set of vector instructions, the compiler converted the loop to the set of vector instructions, an error may be included in an executed result.